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Journal:
X. Chen, H. Hsieh,
and F. Balarin, "Verification Approach of Metropolis Design
Framework for Embedded Systems", International
Journal of Parallel Programming, Special Issue of Testing of
Embedded Systems, Kluwer Academic Publishers, 2005. X. Chen, Y. Luo, H.
Hsieh, L. Bhuyan and F. Balarin, "Assertion-Based
Verification and Analysis of Network Processor
Architectures", International Journal of Design Automation
for Embedded Systems, Kluwer Academic Publishers, 2005. X. Chen, H. Hsieh,
F. Balarin, and Y. Watanabe, "Logic of Constraints: A
Quantitative Performance and Functional Constraint
Formalism",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
23(8), August 2004. [PDF] -
X.
Chen, H. Hsieh, F. Balarin, and Y. Watanabe, "Formal
Verification for Embedded System Designs", International Journal of Design Automation for Embedded Systems, Special Issue of
Covalidation of Embedded Hardware/Software System , edited
by Ian G. Harris, Kluwer Academic Publishers, 8(2/3),
June/September 2003. [PDF]
Y. Luo, L. Bhuyan,
X. Chen, "Shared Memory Multiprocessor Architectures for
Software IP Routers",
IEEE Transactions on Parallel and Distributed Systems,
14(12), December 2003. [PDF]
Conference:
X. Chen, A. Davare,
H. Hsieh, A. Sangiovanni-Vincentelli, and Y. Watanabe, "Simulation-Based Deadlock Analysis for System Level
Designs",
in Proceedings of Design Automation Conference (DAC
'05), Anaheim, CA, June 2005. J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang,
and F. Balarin. "Assertion-Based Design Exploration of DVS in Network Processor Architectures",
in Proceedings of Design Automation and Test in Europe (DATE
'05), Munich, Germany, March, 2005. J. Yu, W. Wu, X.
Chen, H. Hsieh, J. Yang, and F. Balarin, "Assertion-Based
Power/Performance Analysis of Network Processor
Architectures",
in Proceedings of International Workshop on High Level Design Validation and Test
(HLDVT '04), Sonoma Valley, CA, November 2004. [PDF] X. Chen, Y. Luo, H.
Hsieh, L. Bhuyan, and F. Balarin, "Utilizing Formal
Assertions for System Design of Network Processors",
in Proceedings of Design Automation and Test in Europe
(DATE '04), Designers’ Forum, Paris, France, February 2004. [PDF] X. Chen, H. Hsieh,
F. Balarin, and Y. Watanabe, "Verifying LOC Based
Functional and Performance Constraints",
in Proceedings of International Workshop on High Level Design Validation and Test
(HLDVT '03), San Francisco, CA, November 2003. [PDF] X.
Chen, H. Hsieh, F. Balarin, and Y. Watanabe, "Automatic
Trace Analysis for Logic of Constraints", in Proceedings of Design
Automation Conference (DAC '03), Anaheim, CA, June 2003. [PDF] -
X.
Chen, H. Hsieh, F. Balarin, and Y. Watanabe, "Case
Studies of Model Checking for Embedded System Designs", in Proceedings of the Third International Conference on Application of
Concurrency to System Design (ACSD '03), Guimarães, Portugal,
June 2003. [PDF]
-
X.
Chen, H. Hsieh, F. Balarin, and Y. Watanabe, "Automatic
Generation of Simulation Monitors from Quantitative Constraint
Formula", in Proceedings of
Design Automation and Test in Europe (DATE '03), Munich,
Germany, March 2003. [PDF]
-
X.
Chen, F. Chen, H. Hsieh, F. Balarin, and Y. Watanabe,
"Formal Verification of Embedded System Designs at
Multiple Levels of Abstraction", in Proceedings of International Workshop on High Level Design
Validation and Test (HLDVT '02), Cannes, France, October 2002. [PDF]
Book Chapter:
X.
Chen, H. Hsieh, F. Balarin, and Y. Watanabe, "Simulation
Trace Verification For Quantitative Constraints", Embedded
Software for SoC, edited by Ahmed A. Jerraya, Sungjoo Yoo,
Norbert When, Diederik Verkest, Kluwer Academic
Publishers, June 2003. [PDF]
Technical
Report:
X. Chen, H. Hsieh,
F. Balarin, and Y. Watanabe, "Logic of Constraints: A
Quantitative Performance and Functional Constraint
Formalism",
Technical Report UCR-CS-04-87, University of California,
Riverside, 2004. [PDF]
Ph.D.
Thesis:
-
"Verification
and Analysis of System Designs with Functional and
Performance Constraints", University of California,
Riverside, August 2005. [PDF]
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