In the previous assignment, you designed the multicylce MIPS datapath used for integer operations. In this assignment, you will design the controller that operates the datapath.
For this project, you will be implementing the finite state machine shown on page 344 in Figure 5.40. The states shown in the figure specify the values of signals of each state. Make sure that signals not specified for a particular state are not asserted.
In addition to the controller, you must implement the ALU control and all other logic shown in green on page 344 in figure 5.39. Chapter five discusses the specifics for the ALU control.
This project will be tested in a similar manner as the previous project. You will be given a testbench that tests for correct output.
The MIPS entity is used to combine the datapath and control units. You will need to modify this file in order to connect the datapath, control, and alu control. The Control entity is implements everything shown in green except for the ALUControl. The ``or gate'' and ``and gate'' shown in Figure 5.33 should be included in the Control entity. The ALU control is used to implement the alu control shown in Figure 5.33.
DO NOT CHANGE THE ENTITY DECLARATIONS AT ALL! In this assignment, you only need to modify the architectures. If the entity needs to be changed, it will be provided to the entire class.
The testbench and memory have been added to the links of provided code. The testbench will be used for grading in the same way as the previous project. Make sure you download the new memory entity, even if you use the provided solution to the datapath. It contains a slightly different program than before. The PCWrite and PCWriteCond signals should be internal signals within the Control entity. Therefore, the gates shown in Figure 5.33 should be inside the Control entity and the results from these gates should be connected to the PC_load output.