Processors consist of two main components: a controller and a datapath. The datapath handles all required arithmetic computations. The controller is responsible for telling the datapath what to do, based on the instructions in the executing program.
Datapaths typically contain a register file in order to store data, whose outputs are connected to the inputs of an ALU (arithmetic logic unit). Therefore, a controller can achieve a specific computation by reading values from the register file and telling the ALU to perform a specific operation. The result of the ALU can then be stored back into the register file. Generally, actual datapaths are more complicated in order to implement all operations needed by an instruction set.
In this assignment you will implement the datapath shown in Figure 5.39 on page 344 of your book in VHDL. You must implement entities for the register file, multiplexors, sign extendor, shifter, ALU, any additional registers, and any other required components. Do not implement any of the control entities (these are shown in green on the figure).
The entity and architecture declaration for the datapath are provided HERE.
DO NOT CHANGE THE ENTITY DECLARATION! A common interface is required for testing. If for some reason the entity needs to be changed, a new file will be provided to the entire class. The PCWriteCond and PCWrite signals are replaced by a single PCLoad input. The logic required for PCLoad will also be implemented in the next assignment.
There are several outputs in the datapath entity with names that start with testing_. Simply connect the appropriate internal signals to these outputs. These are needed in order to check the values in the testbench.
Make sure to connect the testing output signals in the datapath entity to the appropriate internal signals. Testing_mem_data should be connected to the output from memory. Testing_alu_result should be connected to the output from the ALU. Testing_read_data_1/2 should be connected to the read output from the register file. For example, if you have an internal signal ``mem_data'' which is connected to the output of memory, you could connect it to the testing_mem_data signal in the following way: testing_mem_data <= mem_data; Put this statement anywhere in the architecture of the datapath, between the begin and end statements.
Two files: memory.vhd and testbench.vhd are provided for you to test your programs. These will be used to grade your projects so make sure you get your project working with these files. You can modify the files for your own testing, but it must work with the provided files. The register file required by the datapath has some specific details which must be followed in order for your designs to match the proper timing specified by the book. All reads are asynchronous, which implies that a clock is not required for reads. However, writes must be clocked. Details for the register file are given on page B-25 in the appendix. Refer to the provided memory entity for similar functionality.
It is highly recommended that you read Ch.5 before starting this project, even if it has not yet been covered in class.