32-bit Partitioned ALU

Design and implement a partitioned 32-bit ALU as shown in Fig. 1

Figure 1: A Partitioned 32-bit ALU

The ALU has at least the following features:

• addition of signed integer numbers
• subtraction of signed integer numbers
• negation of signed integer numbers
• signals for overflow
• control bit to select 16-bit or 32-bit ALU operations.

In addition, you are required to write a testbench, which has at least the following testcases:

• a positive number plus a positive number, resulting overflow
• a negative number plus a negative number, resulting overflow
• a positive number minus a negative number, resulting overflow
• a negative number minus a positive number, resulting overflow
• partitioned ALU operations including 16-bit addition, subtraction and NOT

Hints:
The most confusing part will be the overflow checking. What is overflow? When will that happen?

Refer to Fig 3.3 on page 172 of the textbook.

In-lab lecture notes:

• A 2-to-4 decoder circuit.
• Entity declaration
• Structural Style of Modeling: Entity is described as a set of interconnected components.
• Dataflow Style: the flow of data through the entity is expressed primarily using concurrent signal assignment statements.
• Behavioral Style: specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order (in a process statement).
• Signal vs Variable
• Testbench

References:
1. Weijun Zhang, VHDL Tutorial: Learn by Example, http://www.cs.ucr.edu/content/esd/labs/tutorial/
2. J. Bhasker, VHDL Primer 3rd Ed., Prentice Hall 1999