Unix Password Cracking Using FPGAs

The code below is from my senior undergrad project, a brute force UNIX password cracker implemented in VHDL. The code was synthesized using Xilinx ISE and implemented on a Xilinx Virtex XCV1000 FPGA development board. The cracker is capable of running at 25MHz, testing 25 million keys per second. This is approximately 13 times faster than an optimized software implementation running on a 1.4 Ghz Athlon PC.

See here for an overview of how the crypt() utility works in UNIX. The traditional implementation of crypt is a modification of the DES algorithm. crypt is run with key and salt inputs to produce a hash. This hash is then stored in /etc/passwd (or /etc/shadow) for password authentication. A brute force cracking attempt can be made by running crypt on an entire keyspace until finding the correct hash output.

DES code from The Free IP Project (now defunct?) was used as the starting point for this project.