-- Shawn Nematbakhsh -- UNIX DES Password Cracker -- Clock divider for LCD / uC clock library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; entity div is port( clk: in std_logic; rst: in std_logic; clk_out: out std_logic); end div; --}} End of automatically maintained section architecture arch of div is signal a : UNSIGNED(7 downto 0); signal clk_sig : std_logic; signal data_shift : std_logic_vector(55 downto 0); begin process(clk,rst) begin if(rst='1') then a <= "00000000"; clk_out <= '0'; clk_sig <= '0'; elsif(clk='1' and clk'event) then if(a = conv_unsigned(255,8)) then a <= "00000000"; clk_sig <= not clk_sig; clk_out <= clk_sig; else a <= a + '1'; end if; end if; end process; end arch;