Home Research Teaching Vita

Journal:

  1. Y. Luo, J. Yu, J. Yang and L. Bhuyan,"Conserving Network Processor Power Consumption By Exploiting Traffic Variability", accepted by ACM Transactions on Architecture and Code Optimization (TACO), 2006.

  2. J. Yang, J. Yu and Y.T. Zhang, "A Low Energy Cache Design for Multimedia Applications Exploiting Set Access Locality", Journal of Systems Architecture (JSA), Vol.51, No.10-11, October-November, 2005.

Conference:

  1. J. Yu, J.N. Yao, L. Bhuyan and J. Yang, "Program Mapping onto Network Processors by Recursive Bipartitioning and Refining", submitted to 44th Design Automation Conference (DAC '07), San Diego, CA, June 2007.  

  2. J. Yu, J. Yang, S.J. Chen, Y. Luo, L. Bhuyan, "Enhancing Network processor Simulation Speed With Statistical Input Sampling ", in proceedings of International Conference on High Performance Embedded Architectures & Compilers (HiPEAC '05), Barcelona, Spain, November, 2005.  

  3. Y. Luo, J. Yu, J. Yang, L. Bhuyan, "Low Power Network Processor Design using Clock Gating", in proceedings of 42th Design Automation Conference (DAC '05), Anaheim, CA, June. 2005.  

  4. J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang and F. Balarin, "Assertion-Based Automatic Design Exploration of DVS in Network Processor Architecture", in proceedings of Design Automation and Test in Europe (DATE '05), Munich, Germany, March, 2005.  

  5. J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang and F. Balarin, "Assertion-Based Power/Performance Analysis of Network Processor Architecture", in proceedings of International Workshop on High Level Design Validation and Test (HLDVT '04), Sonoma Valley, CA, November, 2005.  

  6. J. Yang, J. Yu, Y.T. Zhang, "Lightweight Set Buffer: Low Power Data Cache for Multimedia Applications", in proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '03), Seoul, Korea, August, 2003.  

  7. L. Y. Zhou, B. Yu, J. Yu, "Light Path Protection for IP/DWDM Networks", in proceedings of International Conference on Optical Communications and Networks (ICOCN '02), Singapore, November, 2002.  

Master Thesis:

  1. J. Yu and J. Yang ,"Low Power Loop Trace Cache Design", University of California, Riverside, December, 2004.