CS161L Design and
Architecture of Computer Systems Laboratory
Term:
2006
Spring
Instructor: Walid Najjar
Classpage: CS161L
Office Hour: Tue. 2:30pm~3:30pm room 110 EBUII or by appointment
- Course Discription
- This is a more advanced class for students who are intending to
purse their degrees in engineering and sciences. Before taking this
class, students are required to have a basic idea about VHDL language
or Verilog Language and classic concept in computer architecture and
design.
- In this class, we are going to use Active-HDL to simulate VHDL
design code on combinitional logic, then analyze the result.
- It is encouraged to use the course webpage on moodle, where we publish the
assignment for each individual lab. To use moodle, please click on the here, and select CS161L from
the course list, then either choose to visit as a guest or enroll in
the class.
- References
- There are a lot of useful references on moodle, where you could
simply download and study. Meanwhile, I would also like to write some
simple tutorials for your information.
- Lab 1 Introduction to
Active HDL (Courtesy of Abhisheck)
- Lab 2