Homework 5
7.9 Here is a seris of address references given as word addresses:
2, 3, 11, 16, 21, 13, 64, 48, 19, 11, 3, 22, 4, 27, 6, 11. Asuming a
direct-mapped cache with 16 one-word blocks that is initially empty, label
each reference in the list as a hit or a miss and show the final contents
of the cache.
7.10 Using the series of address references from the previous exercise,
show the hits and misses and final cache contents for a direct-mapped cache
with four-word blocks and a total size of 16 words.
7.12 Compute the total number of bits required to implement the
cache in Figure 7.9 on page 486. This number is different from the size
of the cache, which usually refers to the number of bytes of data stored in
the cache. The number of bits needed to implement the cache represents the
total amount of memory needed for storing all the data, tags, and valid bits.
7.14 Consider a memory hierarchy using one of the three organizations
for main memory shown in Figure 7.11 on page 489. Assume that the cache block
size is 16 words, that the width of organization (b) of the figure is four
words, and that the number of banks in organization (c) is four. If the main
memory latency for a new access is 10 memory bus clock cycles and the
transfer time is 1 memory bus clock cycle, what are the miss penalties for
each of these organizations?
7.18 and 7.19 can be found here.
7.20 Assume a memory system that supports interleaving either four reads
or four writes. Given the following memory addresses in order as they appear
on the memory bus: 3, 9, 17, 2, 51, 37, 13, 4, 8, 41, 67, 10, which ones will
result in a bank conflict?
7.32 Consider three processors with different cache organizations:
- Cache 1: Direct-mapped with one-word blocks.
- Cache 2: Direct-mapped with four-word blocks.
- Cache 3: Two-way set associative with four-word blocks.
The following miss rate measurements have been made:
- Cache 1: Instruction miss rate is 4%, data miss rate is 6%.
- Cache 2: Instruction miss rate is 2%, data miss rate is 4%.
- Cache 3: Instruction miss rate is 2%, data miss rate is 3%.
For there processors, one-half of the instructions contain a data reference.
Assume that the cache miss penalty is 6 + Block size in words. The CPI for
this workload was measured on a processor with cache 1 and was found to be
2.0. Determine which processor spends the most cycles on cache misses.
7.35 The following C program is run (with no optimizations) on a
processor with a cache that has eight-word (32-byte) blocks and holds 256
bytes of data:
int i, j, c, stride, array[512];
...
for (i=0; i<10000; i++)
for (j=0; j<512; j=j+stride)
c = array[j]+17;
If we consider only the cache activity generated by references on the array and
we assume that integers are words, what is the expected miss rate then the cache
is direct mapped and stride = 256? How about if stride = 255? Would either of
these change if the cache were two-way set associative?
7.39 Consider a virtual memory system with the following properties:
- 40-bit virtual byte address
- 16 KB pages
- 36-bit physical byte address
What is the total size of the page table for each process on this processor,
assuming that the valid, protection, dirty, and use bits take a total of 4 bits
and that all the virtual pages are in use? (Assume that disk addresses are
not stored in the page table.)