Homework 4
5.10 We wish to add the instruction lui (load upper
immediate), as described in Section 2.9 of the text to the single-cycle
datapath described in Chapter 5. Add any necessary datapaths and control
signals to the single-cycle datapath of Figure 5.18 on page 307 of the
text and show the necessary additions to Figure 5.18 on page 308.
5.11 We wish to add a variant of lw (load word instruction)
to the single-cycle datapath described in Chapter 5 of the text. This variant
of lw increments the index register after loading word from memory.
This instruction (let's call it l_inc) corresponds to the following
two instructions:
lw $rs, L($rt)
addi $rt, $rt, 1
Add any necessary datapaths and control signals to the single-cycle datapath
of Figure 5.18 on page 307 of the text and show the necessary additions to
Figure 5.18 on page 308.
5.13 Consider the signe-cycle datapath in Figure 5.17. A friend is proposing
to modify this single-cycle datapath by eliminating the control signal MemtoReg.
The multiplexor that has MemtoReg as an input will instead use either the ALUSrc
or the MemRead control signal. Will your friend's modification work? Can one of
the two signals (MemRead and ALUSrc) substitute for the other? Explain.
5.28 The concept of the "critical path," the longest possible path in
the machine, was introduced in 5.4 on page 315. Based on your understanding
of the single-cycle implementation, show which units can tolerate more
delays (i.e., are not on the critical path), and which units can benefit from
hardware optimization. Quantify your answers taking the same numbers presented
on page 315 (Section 5.4, "Example: Performance of Single-Cycle Machines").
5.35 Consider a change to the multiple-cycle imlementation that alters
the register file so that it has only one read port. Describe (via a diagram)
any additional changes that will need to be made to the datapath in order to
support this modification. Modify the finite state machine to indicate how the
instructions will work, given your new datapath.