-- Albert Coba 1727
  -- Shawn Nematbakhsh 8551			
  
  -- cs161 proj2: control:
  -- a MIPS control
  
-- this file combines the ALU control, the Control, and the datapath
-- to create the MIPS computer
  
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity MIPS is
    port(
        rst : in std_logic;
		clk : in std_logic;

        -- used for testing
        testing_alu_result    : out std_logic_vector(31 downto 0);
        testing_mem_data      : out std_logic_vector(31 downto 0);
        testing_read_data_1   : out std_logic_vector(31 downto 0);
        testing_read_data_2   : out std_logic_vector(31 downto 0);
        testing_ins_31_26     : out std_logic_vector( 5 downto 0)
        );
    
end MIPS;

-- purpose: put all the components together
architecture str of MIPS is

component Datapath
    port(
    
	rst : in std_logic;
	clk : in std_logic;

        --control signals
	alu_src_A : in std_logic;
	alu_src_B : in std_logic_vector( 1 downto 0 );
        -- output from the ALU control shown in Figure 5.33
	alu_control : in std_logic_vector( 2 downto 0 );
	reg_write : in std_logic;
	reg_dst : in std_logic;
	pc_source : in std_logic_vector( 1 downto 0 );
    -- output from the or gate, combining PCWriteCond and PCWrite
    pc_load : in std_logic;
	i_or_d : in  std_logic;
	mem_read : in std_logic;
	mem_write : in std_logic;
	mem_to_reg : in std_logic;
	IR_write : in  std_logic;
        
    -- output to controller
	ins_31_26 : out std_logic_vector( 5 downto 0 );
    -- output to ALU control
   	ins_5_0   : out std_logic_vector( 5 downto 0 );
    -- output to PC write logic
    alu_zero   : out std_logic;

    -- used for testing
    testing_alu_result    : out std_logic_vector(31 downto 0);
    testing_mem_data      : out std_logic_vector(31 downto 0);
    testing_read_data_1   : out std_logic_vector(31 downto 0);
    testing_read_data_2   : out std_logic_vector(31 downto 0)
);
    
end component;

component Control
    port(
    rst : in std_logic;
	clk : in std_logic;

    --control signals
	alu_src_A : out std_logic;
	alu_src_B : out std_logic_vector( 1 downto 0 );
	alu_op : out std_logic_vector( 1 downto 0 );
	reg_write : out std_logic;
	reg_dst : out std_logic;
	pc_source : out std_logic_vector( 1 downto 0 );
    -- output from the or gate, combining PCWriteCond and PCWrite
    pc_load : out std_logic;
	i_or_d : out  std_logic;
	mem_read : out std_logic;
	mem_write : out std_logic;
	mem_to_reg : out std_logic;
	IR_write : out std_logic;
        
    -- input to control
	ins_31_26 : in std_logic_vector( 5 downto 0 );
    -- input to PC write logic
    alu_zero   : in std_logic
);
    
end component;

component ALUControl
    port(
	alu_op : in std_logic_vector( 1 downto 0 );
   	ins_5_0   : in std_logic_vector( 5 downto 0 );
    alu_control : out std_logic_vector( 2 downto 0 )
);
    
end component;

-- out from control, to datapath
signal s_alu_src_A :  std_logic;
signal s_alu_src_B :  std_logic_vector( 1 downto 0 );
signal s_reg_write :  std_logic;
signal s_reg_dst :  std_logic;
signal s_pc_source :  std_logic_vector( 1 downto 0 );
signal s_pc_load :  std_logic;
signal s_i_or_d :   std_logic;
signal s_mem_read :  std_logic;
signal s_mem_write :  std_logic;
signal s_mem_to_reg :  std_logic;
signal s_IR_write :  std_logic;

-- out from control, to alu control
signal s_alu_op :  std_logic_vector( 1 downto 0 );

-- out from datapath, to control
signal s_ins_31_26:  std_logic_vector(5 downto 0);
signal s_alu_zero: std_logic;

-- out from datapath, to alu control
signal s_ins_5_0:  std_logic_vector(5 downto 0);

-- out from alu control, to datapath
signal s_alu_control: std_logic_vector(2 downto 0);

-- testing signals, out from datapath
signal s_testing_alu_result:  std_logic_vector(31 downto 0);
signal s_testing_mem_data:  std_logic_vector(31 downto 0);
signal s_testing_read_data_1:  std_logic_vector(31 downto 0);
signal s_testing_read_data_2:  std_logic_vector(31 downto 0);

begin  -- bhv
	
	-- control unit
	CTRL: Control port map(rst,clk,s_alu_src_A,s_alu_src_B,s_alu_op,s_reg_write,s_reg_dst,
	s_pc_source,s_pc_load,s_i_or_d,s_mem_read,s_mem_write,s_mem_to_reg,s_IR_write,
	s_ins_31_26,s_alu_zero);
	
	-- alu control
	ALUCTRL: ALUControl port map(s_alu_op,s_ins_5_0,s_alu_control);	
	
	-- datapath
	DP: Datapath port map(rst,clk,s_alu_src_A,s_alu_src_B,s_alu_control,s_reg_write,
	s_reg_dst,
	s_pc_source,s_pc_load,s_i_or_d,s_mem_read,s_mem_write,s_mem_to_reg,s_IR_write,
	s_ins_31_26,s_ins_5_0,s_alu_zero,s_testing_alu_result,s_testing_mem_data,
	s_testing_read_data_1,s_testing_read_data_2);
	
	-- assign testing variables
	testing_alu_result<=s_testing_alu_result;
	testing_mem_data<=s_testing_mem_data;	
	testing_read_data_1<=s_testing_read_data_1;
	testing_read_data_2<=s_testing_read_data_2;
	testing_ins_31_26 <=s_ins_31_26;
 
 
  
end str;