-- Albert Coba 1727
  -- Shawn Nematbakhsh 8551			
  
  -- cs161 proj1: Datapath:
  -- a MIPS datapath


-- Datapath
--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity Datapath is
    port(
        rst : in std_logic;
	clk : in std_logic;

        --control signals
	alu_src_A : in std_logic;
	alu_src_B : in std_logic_vector( 1 downto 0 );
        -- output from the ALU control shown in Figure 5.33
	alu_control : in std_logic_vector( 2 downto 0 );
	reg_write : in std_logic;
	reg_dst : in std_logic;
	pc_source : in std_logic_vector( 1 downto 0 );
        -- output from the or gate, combining PCWriteCond and PCWrite
        pc_load : in std_logic;
	i_or_d : in  std_logic;
	mem_read : in std_logic;
	mem_write : in std_logic;
	mem_to_reg : in std_logic;
	IR_write : in  std_logic;
        
        -- output to controller
	ins_31_26 : out std_logic_vector( 5 downto 0 );
        -- output to ALU control
    	ins_5_0   : out std_logic_vector( 5 downto 0 );
        -- output to PC write logic
        alu_zero   : out std_logic;

        -- used for testing
        testing_alu_result    : out std_logic_vector(31 downto 0);
        testing_mem_data      : out std_logic_vector(31 downto 0);
        testing_read_data_1   : out std_logic_vector(31 downto 0);
        testing_read_data_2   : out std_logic_vector(31 downto 0)
        );
    
end Datapath;

-- purpose: put all the components together
architecture bhv of Datapath is

component Memory
    port( 
	rst        : in  std_logic;
        clk	   : in  std_logic;        
	rd         : in  std_logic;
	wr         : in  std_logic;
	addr       : in  std_logic_vector (31 downto 0);
	in_data    : in  std_logic_vector (31 downto 0);
	out_data   : out std_logic_vector (31 downto 0)
	);
end component;

component Mux2_5 is
port(
	rst : in std_logic;
	clk : in std_logic;
	sel : in std_logic;
	in1 : in std_logic_vector(4 downto 0);
	in2 : in std_logic_vector(4 downto 0);
	output : out std_logic_vector(4 downto 0));
end component;

component Mux2 is
	port(
	rst : in std_logic;
	clk : in std_logic;
	sel : in std_logic;
	in1 : in std_logic_vector(31 downto 0);
	in2 : in std_logic_vector(31 downto 0);
	output : out std_logic_vector(31 downto 0));
end	component;

component Mux4 is
  port(
  	rst : in std_logic;
    clk : in std_logic;
    sel : in std_logic_vector(1 downto 0);
	in1 : in std_logic_vector(31 downto 0);
  	in2 : in std_logic_vector(31 downto 0);
	in3 : in std_logic_vector(31 downto 0);
	in4 : in std_logic_vector(31 downto 0);
	output : out std_logic_vector(31 downto 0));
end component;

component IR is
  port(
  	rst : in std_logic;
  	clk : in std_logic;
	MemData : in std_logic_vector(31 downto 0);
	IRWrite : in std_logic;
	output  : out std_logic_vector(31 downto 0));
end component;

component Register32 is
  port(
    rst : in std_logic;
  	clk : in std_logic;
	RegWrite : in std_logic;
	ReadReg1 : in std_logic_vector(4 downto 0);
	ReadReg2 : in std_logic_vector(4 downto 0);
    WriteReg : in std_logic_vector(4 downto 0);
	WriteData: in std_logic_vector(31 downto 0);
	ReadData1 : out std_logic_vector(31 downto 0);
	ReadData2 : out std_logic_vector(31 downto 0));
end component;

component Register1 is
	port(
		rst : in std_logic;
		clk : in std_logic;
		DataIn : in std_logic_vector(31 downto 0);
		DataOut: out std_logic_vector(31 downto 0));
end component;

component ALU is
	port(
		rst : in std_logic;
		clk : in std_logic;
		ctrl: in std_logic_vector(2 downto 0);
		in1 : in std_logic_vector(31 downto 0);
		in2 : in std_logic_vector(31 downto 0);
		output : out std_logic_vector(31 downto 0);
		zero : out std_logic);
end component;

component SignExtender is
	port(
	  rst : in std_logic;
	  clk : in std_logic;
	  input: in std_logic_vector(15 downto 0);
	  output : out std_logic_vector(31 downto 0));
end component;

component Shift32 is
	port( 
		clk: in std_logic;
		rst: in std_logic;
		input: in std_logic_vector(31 downto 0);
		output: out std_logic_vector(31 downto 0));
end component;

component Shift28 is
port(
	rst: in std_logic;
	clk: in std_logic;
	input: in std_logic_vector(25 downto 0);
	output: out std_logic_vector(27 downto 0));
end component;

-- output of PC
signal PC_OUT: std_logic_vector(31 downto 0);
-- memory address, connect to output of MUX
signal address   : std_logic_vector(31 downto 0);
-- data to write to memory, connect to output of B register
signal write_data : std_logic_vector(31 downto 0);
-- data read from Memory, connect to input of IR and MDR
signal mem_data   : std_logic_vector(31 downto 0);
-- output of IR, gets split A LOT
signal IR_OUTPUT  : std_logic_vector(31 downto 0);
-- output of MDR, goes to a mux
signal MDR_OUTPUT : std_logic_vector(31 downto 0);
-- output from mux to write data line on reg32
signal WRITE_DATA_IN: std_logic_vector(31 downto 0);
-- out from	mux, register to write to on big RF
signal WRITE_REGISTER: std_logic_vector(4 downto 0);
-- outputs of the reg32
signal BIG_REG_OUT1: std_logic_vector(31 downto 0);
signal BIG_REG_OUT2: std_logic_vector(31 downto 0);
-- outputs of delay registers A and B
signal REG_A_OUT: std_logic_vector(31 downto 0);
signal REG_B_OUT: std_logic_vector(31 downto 0);
-- output of sign extender
signal SIGN_EXTENDED_OUT: std_logic_vector(31 downto 0);
-- output of 32 bit shifter on bottom
signal SHIFT_32_OUT: std_logic_vector(31 downto 0);
-- inputs to ALU
signal ALU_IN_1: std_logic_vector(31 downto 0);
signal ALU_IN_2: std_logic_vector(31 downto 0);
-- out of ALU
signal ALU_OUT: std_logic_vector(31 downto 0);
-- out of 26 --> 28 shifter
signal SHIFT_28_OUT: std_logic_vector(27 downto 0);
-- calc the addr to jump to
signal JUMP_ADDR: std_logic_vector(31 downto 0);
-- the output of the ALUOut register
signal ALU_OUT_REG_OUT: std_logic_vector(31 downto 0);
-- input to PC, out of last mux
signal PC_IN: std_logic_vector(31 downto 0);

begin  -- bhv


  -- put everything together:: 
  U_MEM : Memory port map (rst,
                           clk,
                           mem_read,
                           mem_write,
                           address,
                           REG_B_OUT,
                           mem_data);	
  IR_FROM_MEM : IR port map(rst,clk,mem_data,IR_write,IR_OUTPUT);
  
  MDR : Register1 port map(rst,clk,mem_data,MDR_OUTPUT);  
  
  WRITE_DATA_IN_MUX: Mux2 port map(rst,clk,mem_to_reg,ALU_OUT_REG_OUT,
  MDR_OUTPUT,WRITE_DATA_IN);
  
  WRITE_REGISTER_IN_MUX: Mux2_5 port map(rst,clk,reg_dst,IR_OUTPUT(20 downto 16),IR_OUTPUT(15 downto 11),WRITE_REGISTER);
  
  BIG_FAT_REG: Register32 port map(rst,clk,reg_write,IR_OUTPUT(25 downto 21),
  IR_OUTPUT(20 downto 16),WRITE_REGISTER,WRITE_DATA_IN,BIG_REG_OUT1,BIG_REG_OUT2);
  
  REG_A: Register1 port map(rst,clk,BIG_REG_OUT1,REG_A_OUT);
  REG_B: Register1 port map(rst,clk,BIG_REG_OUT2,REG_B_OUT);
  
  SIGN_EXTENDR: SignExtender port map(rst,clk,IR_OUTPUT(15 downto 0),SIGN_EXTENDED_OUT);
  SIGN_SHIFT: Shift32 port map(clk,rst,SIGN_EXTENDED_OUT,SHIFT_32_OUT);
  
  ALU_IN_MUX1: Mux2 port map(rst,clk,alu_src_a,PC_OUT,REG_A_OUT,ALU_IN_1);
  ALU_IN_MUX2: Mux4 port map(rst,clk,alu_src_b,REG_B_OUT,"00000000000000000000000000000100",
  SIGN_EXTENDED_OUT,SHIFT_32_OUT,ALU_IN_2);
  
  BIG_ALU: ALU port map(rst,clk,alu_control,ALU_IN_1,ALU_IN_2,ALU_OUT,alu_zero);
  
  SHIFT26_28: Shift28 port map(rst,clk,IR_OUTPUT(25 downto 0),SHIFT_28_OUT);
  
  -- code to calc jump addr
  JUMP_ADDR(31 downto 28) <= PC_OUT(31 downto 28);
  JUMP_ADDR(27 downto 0) <= SHIFT_28_OUT;
  
  ALU_OUT_REG: Register1 port map(rst,clk,ALU_OUT,ALU_OUT_REG_OUT);
  
  LAST_MUX: Mux4 port map(rst,clk,pc_source,ALU_OUT,ALU_OUT_REG_OUT,JUMP_ADDR,
  "01010101010101010101010101010101",PC_IN);
  
  PC: IR port map(rst,clk,PC_IN,pc_load,PC_OUT);
  
  MUX_FEEDING_MEM: Mux2 port map(rst,clk,i_or_d,PC_OUT,ALU_OUT_REG_OUT,address);

  ins_31_26 <= IR_OUTPUT(31 downto 26);
  ins_5_0 <= IR_OUTPUT(5 downto 0);
  testing_alu_result   <= ALU_OUT;
  testing_mem_data     <= mem_data;
  testing_read_data_1   <= BIG_REG_OUT1;
  testing_read_data_2   <= BIG_REG_OUT2;

end bhv;