--som neema
-- 08/20/2004

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity toplevel is
port(
clk : in std_logic;
rst : in std_logic;
start: in std_logic;
finished : out std_logic;
number : out integer;
color : out std_logic_vector(1 downto 0)
);
end toplevel;

architecture structure of toplevel is

signal en  : std_logic;
signal num : integer;
signal col : std_logic_vector(1 downto 0);

component rcounter 
port(
rst : in std_logic;
clk : in std_logic;
roulnum : out integer;
roulcol : out std_logic_vector(1 downto 0)
);
end component;

component spinner
	port(
		clk : in std_logic;
		rst : in std_logic;
		start : in std_logic;
		outclock : out std_logic;
		finished : out std_logic );
end component;

component roulreg 
port(
rst : in std_logic;
en	  : in std_logic;
roulnum : in integer;
roulcol : in std_logic_vector(1 downto 0);
num : out integer;
col : out std_logic_vector (1 downto 0)
);
end component;

begin
u1: rcounter port map (rst, clk, num, col);
u0: spinner port map (clk, rst, start, en, finished);
u2: roulreg port map (rst, en, num, col, number, color);

end structure;