--som neema
-- 08/20/2004


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity spinner is
port(
clk			  : in std_logic;
rst 			  : in std_logic;
start			 : in std_logic;
outclock	: out std_logic;
finished : out std_logic
);
end spinner;

architecture spin of spinner is

signal finishflag: std_logic:='0';
signal tempclock : std_logic :='0';
begin

clkdiv: process(clk, rst, finishflag)
variable i : integer :=9;
begin
if (rst='1' or finishflag ='0') then
outclock <='0';
tempclock <='0';
elsif(finishflag = '1' and clk = '1') then
if (i = 9) then
i := 0;
outclock <= not tempclock;
tempclock <= not tempclock;
else
i :=i + 1;
end if;
end if;
end process;

startup: process(start, rst, tempclock)
variable j: integer:=0;
begin
	if (rst='1') then
		finished <= '0';
		finishflag <= '0';
	elsif (start'event and start <='1') then
		finished<='1';
		finishflag <='1';
	elsif(tempclock'event and tempclock ='1') then
		if (j=5) then
			j:=0;
			finished <='0';
			finishflag <='0';
 		else
			j:=j+1;
 		end if;
	end if;
end process;

end spin;