--som neema
--08/20/2004

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity roulreg is
port(
rst : in std_logic;
en	  : in std_logic;
roulnum : in integer;
roulcol : in std_logic_vector(1 downto 0);
num : out integer;
col : out std_logic_vector (1 downto 0)
);
end roulreg;

architecture roul of roulreg is
begin
comprocess : process(rst, en)
begin
if (rst ='1') then
num <=0;
col <="01";
elsif (en'event and en = '1') then
num <=roulnum;
col <=roulcol;
end if;
end process;
end roul;