--Som Neema 
--08/20/2004

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity rcounter is
port(
rst : in std_logic;
clk : in std_logic;
roulnum : out integer;
roulcol : out std_logic_vector(1 downto 0)
);
end rcounter;

architecture roularch of rcounter is 

constant R : std_logic_vector(1 downto 0):="00";
constant B : std_logic_vector(1 downto 0):="11";
constant G1 : std_logic_vector(1 downto 0):="01";
constant G2 : std_logic_vector(1 downto 0):="10";

signal PC: integer:=1;

type Col_Num is array (1 to 38) of std_logic_vector(7 downto 0);

constant wheelarray : Col_Num := (

"01000000", 				--G00
"00011011",					--R27
"11001010",					--B10
"00011001",					--R25
"11011101",					--B29
"00001100",					--R12
"11001000",					--B8
"00010011",					--R19
"11011111",					--B31
"00010010",					--R18
"11000110",					--B6
"00010101", 				--R21
"11100001",					--B33
"00010000",					--R16
"11000100",					--B4
"00010111",					--R23
"11100011",					--B35
"00001110",					--R14
"11000010",					--B2
"10000000",					--G0
"11011100",					--B28
"00001001",					--R9
"11011010",					--B26
"00011110",					--R30
"11001011",					--B11
"00000111",					--R7
"11010100",					--B20
"00100000",					--R32
"11010001",					--B17
"00000101",					--R5
"11010110",					--B22
"00100010", 				--R34
"11001111",					--B15
"00000011",					--R3
"11011000",					--B24
"00100100",					--R36
"11001101",					--B13
"00000001"					--R1
);

begin

--signal PC : integer;


syn: process(rst, clk)

begin

if (rst='1') then
PC<=1;
elsif (clk'event and clk='1') then
if (PC=38) then
PC<=1;
else
PC<= PC + 1;
end if;
end if;
end process syn;

com: process(PC)
variable temp : std_logic_vector(7 downto 0);
begin

temp :=wheelarray(PC);
roulnum <= conv_integer(temp(5 downto 0));
roulcol <= (temp(7 downto 6));
end process com;

end roularch;