#5,815,728 "processor array" Google Patents

• This is a pin reduction scheme for 2D mesh connected processors that have the property that the x-axis inter-processor connections are never used at the same time as the y-axis connections. The main idea is to not allocate processor cells to chips in the usual rectilinear manner (a rectangular group of processors placed on each chip). Instead, an almost diamond shaped region of processors from the array is placed on each chip. The proposed shapes have the property that the perimeter comprises regions that alternately cut through x-axis connections and y-axis connections, so that the x and y axis connections are paired adjacently along the perimeter. Each pair of connections can be implemented with only a single physical pin/pad, by using multiplexers. This can significantly reduce the number of required pins/chip for such processors. The patent (online, see above) has various diagrams that clarify the improvement.