CS 161 Labs, Winter 2004
TA: Lingling Jin (ljin@cs.ucr.edu)
Office Hours: To be decided
Location: TA office
Lab Assignment 1 (Week 1)
Lab 1.1 ,
1 bit and 4 bit adder
Description:
Code is provided for a
1-bit adder and a corresponding testbench. Steps are given to show students how
to simulate the design. Code is provided for a 4-bit adder built using the 1-bit
adder previously used. A corresponding testbench is also included. Students
simulate the 4-bit adder design and check to see if the functionality is
correct. Covers basic VHDL, behavioral descriptions, structural descriptions,
combinational logic.
Lab 1.2, 2-bit counter
Source Files:
counter.vhd
counter_tb.vhd
Description:
The
purpose of this lab is to write a VHDL description of 2-bit counter as a finite
state machine (FSM). The 2-bit counter has several inputs such as clk, rst,
enable, load, ... and should be able to reset, accept an input, count-up or
count-down, etc...
- Ignore steps for downloading to FPGA.
Useful Information
Active HDL
Tutorial
VHDL Tutorial
and Samples
VHDL References