Eric Cheung
Email: chuncheung at cs dot ucr dot edu
Objective
Seeking an full time position in digital system designs, embedded software, FPGA prototyping, software engineering and C/C++ programming.
Education
Sep 2004 – Aug 2009
University of California, Riverside, CA
Ph.D. Computer Science
GPA: 4.00
Advisor: Prof. Harry Hsieh
Thesis: “MPSoC Simulation and Implementation of KPN Applications”
Sep 2002 – Jun 2004
University of California, Los Angeles, CA
B.S. Computer Science and Engineering
GPA: 3.91
Honor: Summa Cum Laude
Sep 2000 – Jun 2002
De Anza College, Cupertino, CA
Computer Science
GPA: 4.00
Working Experience
Jun 2007 – Sep 2007
Novas Software, San Jose, CA
Summer Intern, R&D Group
Responsible to provide a research prospective on a visibility enhancement engine correlating gate-level signals and register transfer level source codes. Experimental functionalities are implemented on a commercially available EDA tool using C++.
Jun 2006 – Sep 2006
Tensilica Inc., Santa Clara, CA
Summer Intern, Xplorer Group
Responsible to develop and employ a complete nightly distributed regression infrastructure to test the functionalities of a IDE based on Eclipse. Infrastructure is built using Java, Socket, Win32 DLL, XML, and XSLT.
Jun 2005 – Sep 2005
Link_A_Media Device, Santa Clara, CA
Summer Intern, Digital Group
Responsible to develop test plans and regression tests for several components in a SoC design. Integrate Denali memory models into a simulation flow. Additional test modules are modeled using Verilog. Tests are run on a BFM in C and a FPGA prototype. Synopsys VCS are used for simulation, debugging and test coverage.
Teaching Experience
Mar 2007 – Mar 2008
Instructor, University of California, Riverside, CA
Department of Computer Science
Teach upper division computer science classes. Topics include assembly programming, VHDL, hardware design practices, testing methodologies, computer architectures and general processor designs.
Sep 2005 – Present
Research Assistant, University of California, Riverside, CA
Department of Computer Science.
Research focuses on fast performance evaluation and efficient implementation of multimedia applications on handheld devices with multiprocessor on-chip systems. Experiments are done in C++, VHDL and Perl scripts.
Sep 2004 – Present
Teaching Assistant, University of California, Riverside, CA
Department of Computer Science
Supervise undergraduate computer science laboratory sections. Topics include basic Office, C/C++ programming, VHDL, 8051 and AVR microcontrollers, Tornado RTOS, Trimedia DSP, SystemC, Microblaze and Tensilica Xtensa processors. Responsible to create laboratory assignments for better learning experiences.
Jan 2003 – Jun 2004
Reader, University of California, Los Angeles, CA
Department of Electrical Engineering & Department of Physics & Astronomy
Assist in grading homework. Analyze general and specific weaknesses of students.
Technical Skill
Programming Languages: Ansi C, C/C++, STL, Java, Perl, Python, Various assembly languages, OpenGL, Lisp, Scheme, JavaScript, HTML, SQL, XML, XSLT
Digital Designs: Hardware description languages (VHDL, Verilog), SystemC, Xilinx FPGA tools (ISE, EDK), Synopsys tools (VCS, Design Compiler, etc.), Transaction-level modeling
Embedded Systems: Embedded processors (ARM, Tensilica Xtensa, Microblaze), microcontrollers (8051, AVR), DSPs, Real-time O/S (u/C, Tornado)
Computer Architectures: Single and Multi processor architectures, High-performance computing, FPGA, Network-on-chips, System-on-chips
Theories: Algorithms, Time and Space Complexities, P/NP problems, Numerical Computing, Game Theory, Markov Chains, Bayes Theorem
Networks: Network / Socket Programming, TCP/UDP, IP, BGP Routings, Protocol Stack
Operating Systems: Linux, Windows XP/2K/ME/98/95
Applications: Microsoft Office(Word, Excel, PowerPoint), Eclipse, Visual Studio, GCC, GDB, SVN, CVS, Makefile, Emacs
Major School / Research Project
Create a GCC backend for native simulation of embedded processors (C, GCC internal, SystemC)
Accurately estimate software execution time on embedded processors by analyzing its low-level characteristics
Design and prototype a RISC synthesizable multi-cycle soft processor (VHDL, FPGA, Xilinx ISE)
Create a fully functional processor running a subset of RISC instructions on FPGA
Create an ISS simulation model of a pipelined processor with a visualization interface (C++, STL, Qt, Linux)
Allow different combinations of processor elements at runtime and create a Qt interface for the program
Design and implement deadlock detection inside SystemC simulation library kernel (C++, SystemC internal)
Design and implement a efficient algorithm for deadlock detection on an existing open-source C++ library
Model Byzantine Fault Tolerate protocol for scalability evaluation on a network using SSFNet simulator (Java)
Evaluate objectively a protocol in different network topologies by modeling in a realistic network simulator
Implement an efficient and exact longest common subsequence on three strings (C, Linux)
Use software caches to speed up the a dynamic programming algorithm with minor memory overhead
Create a client-server room reservation system using C sockets and multi-thread programming (C, Linux)
Handle multiple client requests using multiple threads with fine-grain resource controls
Research Interest
System-level design: emphasis in simulation, synthesis, embedded systems, hardware/software co-design, low power-design, system-on-chip multi-core architectures, real-time systems, and run-time optimizations.
Publication
Eric Cheung, Harry Hsieh, Felice Balarin. Fast and Accurate Performance Simulation of Embedded Software for MPSoC. Fourteen Asia and South Pacific Design Automation Conference. January 2009.
Eric Cheung, Harry Hsieh, Felice Balarin. Memory Subsystem Simulation in Software TLM/T Models.
Fourteen Asia and South Pacific Design Automation Conference. January 2009.
Eric Cheung, Harry Hsieh, Felice Balarin. Partial Order Method for Timed Simulation of System-Level MPSoC Designs. Fourteen Asia and South Pacific Design Automation Conference. January 2009.
Eric Cheung, Harry Hsieh, Felice Balarin. Software Optimization for MPSoC: A MPEG-2 Decoder Case Study.
Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. October 2008.
Eric Cheung, Harry Hsieh, Felice Balarin. Framework for Fast and Accurate Performance Simulation of Multiprocessor Systems. Twelfth Annual IEEE International Workshop on High Level Design Validation and Test. November 2007.
Eric Cheung, Harry Hsieh, Felice Balarin. Automatic Buffer Sizing for Rate-Constrained KPN Applications on MPSoC. Twelfth Annual IEEE International Workshop on High Level Design Validation and Test. November 2007.
Eric Cheung, Xi Chen, et. al. Bridging RTL and Gate: Correlating Different Levels of Abstraction for Design Debugging. Twelfth Annual IEEE International Workshop on High Level Design Validation and Test. November 2007.
Eric Cheung, Piyush Satapathy, et. al. Runtime Deadlock Analysis of SystemC Design.
Eleventh Annual IEEE International Workshop on High Level Design Validation and Test. November 2006.
Reference
Dr. Harry Hsieh
Assistant Professor
University of California, Riverside, CA
harry at cs dot ucr dot edu
Dr. Frank Vahid
Professor
University of California, Riverside, CA
vahid at cs dot ucr dot edu