Eric Cheung's research mainly focuses on multimedia application designs for multiprocessor system-on-chips, particularly multicore system simulation and profile-based optimizations of Kahn Process Network applications.
Eric Cheung. MPSoC Simulation and Implementation of KPN Applications. Thesis dissertation. August 2009.
Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto Sangiovanni, Yosinori Watanabe. Runtime Deadlock Analysis for System Level Design. Design Automation for Embedded Systems (DAES). Volume 13, Issue 4 (2009), Page 287.
Eric Cheung, Harry Hsieh, Felice Balarin. Fast and Accurate Performance Simulation of Embedded Software for MPSoC. Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC). January 2009.
Eric Cheung, Harry Hsieh, Felice Balarin. Memory Subsystem Simulation in Software TLM/T Models. Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC). January 2009.
Eric Cheung, Harry Hsieh, Felice Balarin. Partial Order Method for Timed Simulation of System-Level MPSoC Designs. Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC). January 2009.
Eric Cheung, Harry Hsieh, Felice Balarin. Software Optimization for MPSoC: A MPEG-2 Decoder Case Study. Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). October 2008.
Eric Cheung, Harry Hsieh, Felice Balarin. Framework for Fast and Accurate Performance Simulation of Multiprocessor Systems. Twelfth Annual IEEE International Workshop on High Level Design Validation and Test (HLDVT). November 2007.
Eric Cheung, Harry Hsieh, Felice Balarin. Automatic Buffer Sizing for Rate-Constrained KPN Applications on Multiprocessor System-on-Chip. Twelfth Annual IEEE International Workshop on High Level Design Validation and Test (HLDVT). November 2007.
Eric Cheung, Xi Chen, Furshing Tsai, Yu-Chin Hsu, Harry Hsieh. Bridging RTL and Gate: Correlating Different Levels of Abstraction for Design Debugging. Twelfth Annual IEEE International Workshop on High Level Design Validation and Test (HLDVT). November 2007.
Eric Cheung, Piyush Satapathy, Vi Pham, Harry Hsieh, Xi Chen. Runtime Deadlock Analysis of SystemC Design. Eleventh Annual IEEE International Workshop on High Level Design Validation and Test (HLDVT). November 2006.